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Disambiguation of "Restle, Phillip J."

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Thermal analysis of multi-layer functional 3D logic stacks.

, , , , , , , , and . 3DIC, page 1-4. IEEE, (2016)

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Alfons Restle

David Restle

Konstantin Restle

Markus Restle

Wilhelm Restle

 

Other publications of authors with the same name

A Resonant Global Clock Distribution for the Cell Broadband Engine Processor., , , , , , , , , and . IEEE J. Solid State Circuits, 44 (1): 64-72 (2009)Loop-based interconnect modeling and optimization approach for multigigahertz clock network design., , , , , and . IEEE J. Solid State Circuits, 38 (3): 457-463 (2003)Loop-based interconnect modeling and optimization approach for multi-GHz clock network design., , , , and . CICC, page 19-22. IEEE, (2002)Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor., , , , , , , , and . ISSCC, page 1-3. IEEE, (2022)5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth., , , , , , , , , and 10 other author(s). ISSCC, page 96-97. IEEE, (2014)Design of Resonant Global Clock Distributions., , and . ICCD, page 248-253. IEEE Computer Society, (2003)New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems., and . ASYNC, IEEE Computer Society, (2005)Subtractive Router for Tree-Driven-Grid Clocks., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (6): 868-877 (2012)Deterministic Frequency and Voltage Enhancements on the POWER10 Processor., , , , , , , , and . IEEE J. Solid State Circuits, 58 (1): 102-110 (2023)The circuit and physical design of the POWER4 microprocessor., , , , , , , , and . IBM J. Res. Dev., 46 (1): 27-52 (2002)