( en | de | ru )

 

Disambiguation of "Kong, Joonho"

Author of the publication

copydeleteadd this publication to your clipboard
Architecting large-scale SRAM arrays with monolithic 3D integration.

, , and . ISLPED, page 1-6. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Thay Kong

Xiangqing Kong

Seunghyun Kong

Deming Kong

Yuanbo Kong

 

Other publications of authors with the same name

Enhancing online power estimation accuracy for smartphones., , and . IEEE Trans. Consumer Electronics, 58 (2): 333-339 (2012)An efficient trade-off between yield and energy for eDRAM caches under process variations., and . Microprocess. Microsystems, (2017)Exploiting narrow-width values for process variation-tolerant 3-D microprocessors., and . DAC, page 1197-1206. ACM, (2012)Selective wordline voltage boosting for caches to manage yield under process variations., , , , and . DAC, page 57-62. ACM, (2009)Row-Wise Product-Based Sparse Matrix Multiplication Hardware Accelerator With Optimal Load Balancing., , , and . IEEE Access, (2022)Linearization Weight Compression and In-Situ Hardware-Based Decompression for Attention-Based Neural Machine Translation., , and . IEEE Access, (2023)Security Issues in Situational Awareness: Adversarial Threats and Mitigation Techniques., , , , and . IEEE Secur. Priv., 20 (4): 51-60 (2022)Characterizing the Thermal Feasibility of Monolithic 3D Microprocessors., , , , , , and . IEEE Access, (2021)AMBITION: Ambient Temperature Aware VM Allocation for Edge Data Centers., , , , and . IEEE Access, (2023)Architecting large-scale SRAM arrays with monolithic 3D integration., , and . ISLPED, page 1-6. IEEE, (2017)