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Reconfigurable self-timed regenerators for wide-range voltage scaled interconnect., , , and . A-SSCC, page 1-4. IEEE, (2015)XPoint cache: scaling existing bus-based coherence protocols for 2D and 3D many-core systems., , , , , , , , and . PACT, page 75-86. ACM, (2012)Parallel high-radix Montgomery multipliers., , and . ACSCC, page 772-776. IEEE, (2008)A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology., , , , , , , , , and 7 other author(s). Hot Chips Symposium, page 1-24. IEEE, (2019)Verifying High-Level Latency-Insensitive Designs with Formal Model Checking., , , , , , and . CoRR, (2021)VerilogEval: Evaluating Large Language Models for Verilog Code Generation., , , and . CoRR, (2023)Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation., , , and . ICCAD, page 1-8. IEEE, (2023)Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation., , , , and . DAC, page 1-2. IEEE, (2023)A 467nW CMOS visual motion sensor with temporal averaging and pixel aggregation., , , , , , and . ISSCC, page 480-481. IEEE, (2013)Impact of FinFET on Near-Threshold Voltage Scalability., , , , , , , , and . IEEE Des. Test, 34 (2): 31-38 (2017)