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Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management.

, , and . ISCAS, page 873-876. IEEE, (2007)

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Message from the chairs., , , and . ReCoSoC, page 1. IEEE, (2015)A dynamic communication strategy for the distributed ATPG system DPLATON., , , and . EURO-DAC, page 271-276. IEEE Computer Society, (1993)Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1057-1061. Springer, (2004)Execution modeling in self-aware FPGA-based architectures for efficient resource management., , , , , and . ReCoSoC, page 1-8. IEEE, (2015)Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support., , , , , and . AHS, page 184-191. IEEE, (2011)Generic Systolic Array for Run-Time Scalable Cores., , , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 4-16. Springer, (2010)Automatic generation of identical routing pairs for FPGA implemented DPL logic., , , and . ReConFig, page 1-6. IEEE, (2012)Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks., , , , , and . Sensors, 12 (3): 2667-2692 (2012)Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing., , , , , and . IEEE Trans. Computers, 62 (8): 1481-1493 (2013)A digital system to emulate wireless networks., , , and . IET Comput. Digit. Tech., 1 (5): 444-450 (2007)