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Models for Embedded Application Mapping onto NoCs: Timing Analysis.

, , , and . IEEE International Workshop on Rapid System Prototyping, page 17-23. IEEE Computer Society, (2005)

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Using evolutionary metaheuristics to solve the mapping and routing problem in networks on chip., , , , and . Des. Autom. Embed. Syst., 27 (1-2): 51-83 (June 2023)Generation of Application Specific Fault Tolerant Irregular NoC Topologies Using Tabu Search., , , and . SBESC, page 1-8. IEEE, (2019)An investigation of latency prediction for NoC-based communication architectures using machine learning techniques., , , and . J. Supercomput., 75 (11): 7573-7591 (2019)Communication Architectures for System-on-Chip., , , and . SBCCI, page 14-19. IEEE Computer Society, (2001)Mapping Wired Links in a Hybrid Wired-Wireless Network-on-Chip., , , , and . SBESC, page 1-8. IEEE, (2020)Machine Learning Based Seismic Region Classification., , , and . IJCNN, page 1-6. IEEE, (2020)Design Space Exploration Using UTNoCs and Genetic Algorithm., , , and . SBESC, page 198-202. IEEE Computer Society, (2016)An Experimental Evaluation of Combination of Features on the IPNoSys., , and . SBESC, page 169-170. IEEE Computer Society, (2013)DDR SDRAM Memory Controller for Digital TV Decoders., , , and . SBESC, page 78-82. IEEE Computer Society, (2011)Design Flow of a Dedicated Computer Cluster Customized for a Distributed Genetic Algorithm Application., , , and . ASAP, page 148-153. IEEE Computer Society, (2007)