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Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse Engineering.

, , and . ACM Great Lakes Symposium on VLSI, page 233-238. ACM, (2017)

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POSTER: BioSEAL: In-Memory Biological Sequence Alignment Accelerator for Large-Scale Genomic Data., , and . PACT, page 459-460. IEEE, (2019)StarSync: An extendable standard-cell mesochronous synchronizer., , , and . Integr., 47 (2): 250-260 (2014)Adaptive programming in multi-level cell ReRAM., , , and . Microelectron. J., (2019)The effect of communication and synchronization on Amdahl's law in multicore systems., , and . Parallel Comput., 40 (1): 1-16 (2014)Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (9): 1243-1248 (2008)Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (4): 427-438 (2005)Relative timing asynchronous design., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (1): 129-140 (2003)A Model for Supply Voltage and Temperature Variation Effects on Synchronizer Performance., and . IEEE Trans. Very Large Scale Integr. Syst., 23 (11): 2461-2472 (2015)A clock-tuning circuit for system-on-chip., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (4): 616-626 (2003)Resistive Associative Processor., , , and . IEEE Comput. Archit. Lett., 14 (2): 148-151 (2015)