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Disambiguation of "Okada, Kenichi"

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24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.

, , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 424-425. IEEE, (2017)

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Kenichi Ishikawa

Kenichi Kida

Kenichi Moriya

Naotake Okada

Hinoto Okada

 

Other publications of authors with the same name

A 20GHz ILFD with locking range of 31% for divide-by-4 and 15% for divide-by-8 using progressive mixing., , and . A-SSCC, page 85-88. IEEE, (2011)An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation., , and . ASP-DAC, page 103-104. IEEE, (2011)The study of the knowledge optimization tool., and . GEC Summit, page 443-450. ACM, (2009)Two-Stage Band-Selectable CMOS Power Amplifiers Using Inter-Stage Frequency Tuning., , , and . IEICE Trans. Electron., 95-C (2): 290-296 (2012)A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI., , , , , and . IEICE Trans. Electron., 100-C (3): 259-267 (2017)Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector., , , , and . IEICE Trans. Electron., 102-C (7): 520-529 (2019)Realistic Delay Calculation Based on Measured Intra-Chip and Inter-Chip Variabilities with the Size Dependence., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (4): 746-751 (2003)Statistical Gate-Delay Modeling with Intra-Gate Variability., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 2914-2922 (2003)A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration., , , , , , , , , and 4 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 603-616 (2021)Eigenmode Analysis of Propagation Constant for a Microstrip Line with Dummy Fills on a Si CMOS Substrate., , , , and . IEICE Trans. Electron., 94-C (6): 1008-1015 (2011)