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Disambiguation of "Silveira, Bianca"

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SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder.

, , , and . ICECS, page 576-579. IEEE, (2015)

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Sarita Silveira

Amelia Silveira

Edilson Silveira

Fernando Silveira Navarra

Nádya Pesce Silveira

 

Other publications of authors with the same name

Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (12): 3126-3137 (2017)A power-efficient 4-2 Adder Compressor topology., , , , , and . NEWCAS, page 281-284. IEEE, (2017)Multi-Size Inverse DCT-II Hardware Design for the VVC Decoder., , , , and . LASCAS, page 1-4. IEEE, (2023)Multiple Transform Selection Hardware Design for 4K@60fps Real-Time Versatile Video Coding., , , , and . ISCAS, page 1-5. IEEE, (2022)A Hardware Design for the Multi-Transform Module of the Versatile Video Coding Standard., , , and . SBCCI, page 1-6. IEEE, (2023)Using adder and subtractor compressors to sum of absolute transformed differences architecture for low-power video encoding., , , , , , , and . ICECS, page 490-493. IEEE, (2017)Low power SATD architecture employing multiple sizes Hadamard Transforms and adder compressors., , , , and . NEWCAS, page 277-280. IEEE, (2017)Power-efficient sum of absolute differences architecture using adder compressors., , , and . ICECS, page 340-343. IEEE, (2016)Low power sum of absolute differences architecture using novel hybrid adder., , , , and . LASCAS, page 1-4. IEEE, (2017)The 4-2 Fused Adder-Subtractor Compressor for Low-Power Butterfly-Based Hardware Architectures., , , , , , and . Circuits Syst. Signal Process., 41 (3): 1577-1595 (2022)