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Disambiguation of "Diniz, Cláudio Machado"

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SATD hardware architecture based on 8×8 Hadamard Transform for HEVC encoder.

, , , and . ICECS, page 576-579. IEEE, (2015)

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Cláudio Walter

Cláudio Faria

Rogério Palhares Diniz

Roberto Antonio Costa Diniz

Carlos Alberto Diniz

 

Other publications of authors with the same name

Algorithm and Hardware Design of a Fast Intra Frame Mode Decision Module for H.264/AVC Encoders., , , , , and . Int. J. Reconfigurable Comput., (2012)Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (6): 2137-2150 (2019)Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors., , , and . SBCCI, page 157-162. ACM, (2010)Adjusting video tiling to available resources in a per-frame basis in High Efficiency Video Coding., , , , and . NEWCAS, page 1-4. IEEE, (2016)VVC Interpicture Prediction Using SAD with Imprecise Subtractors: A Quantitative Analysis., , , , and . ICECS 2022, page 1-4. IEEE, (2022)Power-efficient sum of absolute differences architecture using adder compressors., , , and . ICECS, page 340-343. IEEE, (2016)Exploring power-performance-quality tradeoff of approximate adders for energy efficient sobel filtering., , , , and . LASCAS, page 1-4. IEEE, (2018)Low power sum of absolute differences architecture using novel hybrid adder., , , , and . LASCAS, page 1-4. IEEE, (2017)HEVC Interpolation Filter Architecture Using Hybrid Encoding Arithmetic Operators., , , , , and . MWSCAS, page 331-334. IEEE, (2019)Multi-Size Inverse DCT-II Hardware Design for the VVC Decoder., , , , and . LASCAS, page 1-4. IEEE, (2023)