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Reconfigurable architecture based on FPGA for OFDM transmitter., , and . LATINCOM, page 1-6. IEEE, (2015)A SDR architecture based on FPGA for multi-standard transmitter., , , and . GlobalSIP, page 1266-1269. IEEE, (2013)A Hardware-Efficient Frequency Domain Correlator Architecture for Acquisition Stage in GPS., , , and . ReConFig, page 412-417. IEEE Computer Society, (2010)A Survey of the Graphic Alternate Method for Boolean Functions Simplification., and . CONIELECOMP, page 328-334. IEEE Computer Society, (2005)Iterative MIMO Detection and Channel Estimation Using Joint Superimposed and Pilot-Aided Training., , , and . Mob. Inf. Syst., (2016)A resource efficient symbol synchronizer implementation for the IEEE 802.11 protocol., , , , and . LASCAS, page 1-4. IEEE, (2018)Full-Hardware Architectures for Data-Dependent Superimposed Training Channel Estimation., , , , and . J. Signal Process. Syst., 70 (2): 105-123 (2013)Configurable Transmitter and Systolic Channel Estimator Architectures for Data-Dependent Superimposed Training Communications Systems., , , and . Int. J. Reconfigurable Comput., (2012)Full-hardware architectures for data-dependent superimposed training channel estimation., , , and . SiPS, page 49-54. IEEE, (2011)Architecture Based on Array Processors for Data-Dependent Superimposed Training Channel Estimation., , , and . ReConFig, page 303-308. IEEE Computer Society, (2011)