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Disambiguation of "Tsui, Chi-Ying"

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Gate-level power estimation using tagged probabilistic simulation.

, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (11): 1099-1107 (1998)

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Ying Chi

Chi Lan Tsui

Matthew Tsui

Ying Ying

Tung Yu Tsui

 

Other publications of authors with the same name

An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms., , , , , and . NOCS, page 17-24. IEEE, (2014)A Two-Staged Adaptive Successive Cancellation List Decoding for Polar Codes., , and . ISCAS, page 1-5. IEEE, (2019)Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO., and . VLSI-SoC, page 1-5. IEEE, (2016)A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources., , and . VLSI-SoC, page 192-195. IEEE, (2011)A thermal-aware application specific routing algorithm for Network-on-Chip design., and . ASP-DAC, page 449-454. IEEE, (2011)A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications., and . ISLPED, page 406-411. ACM, (2006)A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture., , , , and . CODES+ISSS, page 161-170. ACM, (2012)Low Power Rake Receiver and Viterbi Decoder Design for CDMA Applications., , and . Wireless Personal Communications, 14 (1): 49-64 (2000)Low-power VLSI design for motion estimation using adaptive pixel truncation., , , and . IEEE Trans. Circuits Syst. Video Techn., 10 (5): 669-678 (2000)The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (8): 1138-1142 (2009)