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Exploring Multi-core Design Space: Heracles vs. Rocket Chip Generator.

, and . J. Comput., 13 (5): 555-563 (2018)

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Optimisation and robustness of cellular neural networks.. Katholieke Universiteit Leuven, Belgium, (2007)base-search.net (ftunivleuven:oai:lirias.kuleuven.be:1979/898).A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core Servers., , , , , and . VLSI-SoC, page 211-216. IEEE, (2019)A QoS and Container-Based Approach for Energy Saving and Performance Profiling in Multi-Core Servers., , , , , , and . VLSI-SoC, page 230-231. IEEE, (2019)Auto Tuning for OpenMP Dynamic Scheduling applied to FWI., , , , , and . CoRR, (2024)When parallel speedups hit the memory wall., , , and . CoRR, (2019)Evaluating the effects of reducing voltage margins for energy-efficient operation of MPSoCs., , , and . CoRR, (2022)Exploring Multi-core Design Space: Heracles vs. Rocket Chip Generator., and . J. Comput., 13 (5): 555-563 (2018)Energy-Optimal Configurations for Single-Node HPC Applications., , , , , and . HPCS, page 448-454. IEEE, (2019)A Scalable Shared-Memory Parallel Simplex for Large-Scale Linear Programming., , and . CoRR, (2018)The Benefits of Low Operating Voltage Devices to the Energy Efficiency of Parallel Systems., , , , , and . CoRR, (2017)