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Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications.

, , , , , and . ASYNC, page 11-18. IEEE Computer Society, (2016)

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A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (9): 858-862 (2016)Testable MUTEX Design., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (8): 1188-1199 (2016)Transistor placement strategies for non-series-parallel cells., , , , , and . MWSCAS, page 523-526. IEEE, (2017)Hermes-A - An Asynchronous NoC Router with Distributed Routing., , , and . PATMOS, volume 6448 of Lecture Notes in Computer Science, page 150-159. Springer, (2010)Adapting a C-element design flow for low power., , , , and . ICECS, page 45-48. IEEE, (2011)Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits., , and . ICECS, page 669-672. IEEE, (2012)Hermes-GLP: A GALS Network on Chip Router with Power Control Techniques., , , and . ISVLSI, page 347-352. IEEE Computer Society, (2008)Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?, , , , , and . ASYNC, page 53-60. IEEE Computer Society, (2014)Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough?, , , and . LATW, page 1-5. IEEE, (2014)Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design., , and . ISQED, page 692-699. IEEE, (2014)