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Parallel subdivision surface rendering and animation on the Cell BE processor.

, , , and . DATE, page 178-183. IEEE Computer Society, (2010)

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Design and Analysis of NoCs for Low-Power 2D and 3D SoCs., , , and . Low Power Networks-on-Chip, Springer, (2011)CAS-CNN: A deep convolutional neural network for image compression artifact suppression., , and . IJCNN, page 752-759. IEEE, (2017)SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs., , , , , , and . CODES+ISSS, page 39-48. ACM, (2011)A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets., , , and . IEEE Trans. Computers, 68 (4): 484-497 (2019)A Minimally Invasive Low-Power Platform for Real-Time Brain Computer Interaction Based on Canonical Correlation Analysis., , , , and . IEEE Internet of Things Journal, 6 (1): 967-977 (2019)Predictability vs. Efficiency in the Multicore Era: Fight of Titans or Happy Ever after?.. CAV, volume 5643 of Lecture Notes in Computer Science, page 50. Springer, (2009)Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms., , and . CASES, page 145-149. ACM, (2007)Dynamic thermal clock skew compensation using tunable delay buffers., , , , , , , and . ISLPED, page 162-167. ACM, (2006)Contents provider-assisted dynamic voltage scaling for low energy multimedia applications., , and . ISLPED, page 42-47. ACM, (2002)Networks on Chips: from research to products., , , , , and . DAC, page 300-305. ACM, (2010)