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Disambiguation of "Suzuki, Daisuke"

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Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack.

, , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (7): 1323-1333 (2016)

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Yoko Suzuki

Daisuke Yoshida

Daisuke Shibata

Daisuke Akimoto

Daisuke Mashima

 

Other publications of authors with the same name

Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices., , and . Microelectron. J., (2019)Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (2): 476-489 (2015)Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow., and . IEICE Trans. Inf. Syst., 104-D (8): 1111-1120 (2021)Timing Black-Box Attacks: Crafting Adversarial Examples through Timing Leaks against DNNs on Embedded Devices., , and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021 (3): 149-175 (2021)Adversarial Black-Box Attacks with Timing Side-Channel Leakage., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 104-A (1): 143-151 (2021)Security Evaluations of MRSL and DRSL Considering Signal Delays., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (1): 176-183 (2008)A Design Methodology for a DPA-Resistant Circuit with RSL Techniques., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2497-2508 (2010)Pulse-Width Modulation with Current Uniformization for TFT-OLEDs., , , , , , and . IEICE Trans. Electron., 90-C (11): 2076-2082 (2007)A high-level synthesis method for simultaneous placement and scheduling considering data communication delay., and . APCCAS (1), page 149-154. IEEE, (2002)A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques., , , and . CHES, volume 5747 of Lecture Notes in Computer Science, page 189-204. Springer, (2009)