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Test Scheduling and Test Access Architecture Optimization for System-on-Chip.

H. Hsu, J. Huang, K. Cheng, C. Wang, C. Huang, C. Wu, and Y. Lin. Asian Test Symposium, page 411-. IEEE Computer Society, (2002)

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Chih-Hong Wang

Chih-Cho Wang

Sheng-Chih Wang

Chih-Chieh Wang

Matei Chihaia

Other publications of authors with the same name

Failure Factor Based Yield Enhancement for SRAM Designs.Y. Hsing, C. Wang, C. Wu, C. Huang, and C. Wu. DFT, page 20-28. IEEE Computer Society, (2004)A built-in self-test and self-diagnosis scheme for embedded SRAM.C. Wang, C. Wu, J. Li, C. Wu, T. Teng, K. Chiu, and H. Lin. Asian Test Symposium, page 45-50. IEEE Computer Society, (2000)STEAC: A Platform for Automatic SOC Test Integration.C. Lo, C. Wang, K. Cheng, J. Huang, C. Wang, S. Wang, and C. Wu. IEEE Trans. Very Large Scale Integr. Syst., 15 (5): 541-545 (2007)A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.C. Wang, R. Tzeng, C. Wu, C. Huang, C. Wu, S. Huang, S. Lin, and H. Wang. Asian Test Symposium, page 103-. IEEE Computer Society, (2001)On-chip interconnection design and SoC integration with OCPC. Wang, C. Lai, C. Wu, S. Hwang, and Y. Lin. VLSI Design, Automation and Test, 2008. VLSI-DAT 2008. IEEE International Symposium on, page 25--28. (abr. 2008)A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.C. Wang, C. Wu, J. Li, C. Wu, T. Teng, K. Chiu, and H. Lin. J. Electron. Test., 18 (6): 637-647 (2002)Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.C. Wu, C. Huang, K. Cheng, C. Wang, and C. Wu. DAC, page 301-306. ACM, (2001)Test Scheduling and Test Access Architecture Optimization for System-on-Chip.H. Hsu, J. Huang, K. Cheng, C. Wang, C. Huang, C. Wu, and Y. Lin. Asian Test Symposium, page 411-. IEEE Computer Society, (2002)Test Scheduling of BISTed Memory Cores for SOC.C. Wang, J. Huang, Y. Lin, K. Cheng, C. Huang, C. Wu, and Y. Lin. Asian Test Symposium, page 356-. IEEE Computer Society, (2002)Error Catch and Analysis for Semiconductor Memories Using March Tests.C. Wu, C. Huang, C. Wang, K. Cheng, and C. Wu. ICCAD, page 468-471. IEEE Computer Society, (2000)

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Disambiguation of "Wang, Chih-Wea"

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Test Scheduling and Test Access Architecture Optimization for System-on-Chip.

Please choose a person to relate this publication to

Chih-Hong Wang

Chih-Cho Wang

Sheng-Chih Wang

Chih-Chieh Wang

Matei Chihaia

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wang, Chih-Wea"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Test Scheduling and Test Access Architecture Optimization for System-on-Chip.

Please choose a person to relate this publication to

Chih-Hong Wang

Chih-Cho Wang

Sheng-Chih Wang

Chih-Chieh Wang

Matei Chihaia

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
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Test Scheduling and Test Access Architecture Optimization for System-on-Chip.