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A 52mW 1200MIPS compact DSP for multi-core media SoC.

S. Ou, T. Lin, C. Huang, Y. Kuo, C. Chao, C. Liu, and C. Jen. ASP-DAC, page 118-119. IEEE, (2006)

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Christopher Tay

Sarab Tay

Lin Lin

Other publications of authors with the same name

A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs.C. Liu, Z. Chang, S. Wei, J. Wang, and T. Lin. SoCC, page 1-6. IEEE, (2018)Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications.P. Chou, Y. Fang, B. Chen, C. Liu, T. Lin, and J. Wang. SoCC, page 250-253. IEEE, (2018)An efficient 2-D DWT architecture via resource cycling.T. Lin, and C. Jen. ISCAS (4), page 914-917. IEEE, (2001)Improving energy efficiency of functional units by exploiting their data-dependent latency.S. Ou, Y. Lin, T. Lin, and C. Liu. ISCAS, page 4165-4168. IEEE, (2010)Variation-aware and adaptive-latency accesses for reliable low voltage caches.P. Wang, W. Cheng, Y. Yu, T. Kao, C. Tsai, P. Chang, T. Lin, J. Wang, and T. Chen. VLSI-SoC, page 358-363. IEEE, (2013)ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures.P. Wang, Y. Chien, S. Tsai, X. Lin, R. Tanjung, Y. Lin, S. Syu, T. Lin, J. Wang, and T. Chen. IEEE Trans. Very Large Scale Integr. Syst., 25 (12): 3341-3354 (2017)Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations.P. Wang, W. Cheng, Y. Yu, T. Kao, C. Tsai, P. Chang, T. Lin, J. Wang, and T. Chen. IEEE Trans. Circuits Syst. II Express Briefs, 63-II (10): 969-973 (2016)Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors.P. Wang, S. Tsai, R. Tanjung, T. Lin, J. Wang, and T. Chen. Integr., (2016)A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods.J. Wang, C. Xue, C. Liu, and T. Lin. ISCAS, page 1-4. IEEE, (2020)A Compact DSP Core with Static Floating-Point Arithmetic.T. Lin, H. Lin, C. Chao, C. Liu, and C. Jen. VLSI Signal Processing, 42 (2): 127-138 (2006)

BibSonomy

Disambiguation of "Lin, Tay-Jyi"

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A 52mW 1200MIPS compact DSP for multi-core media SoC.

Please choose a person to relate this publication to

Christopher Tay

Sarab Tay

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Tay-Jyi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 52mW 1200MIPS compact DSP for multi-core media SoC.

Please choose a person to relate this publication to

Christopher Tay

Sarab Tay

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 52mW 1200MIPS compact DSP for multi-core media SoC.