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Disambiguation of "Kodi, Avinash Karanth"

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Cross-Chip: Low power processor-to-memory nanophotonic interconnect architecture.

, and . IGSC, page 1-6. IEEE Computer Society, (2015)

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Avinash Vyas

Avinash Sudhodanan

Jens Köditz

Sodikdjon Kodirov

Avinash Sidhu

 

Other publications of authors with the same name

Dynamic Power Reduction Techniques in On-Chip Photonic Interconnects., , and . ACM Great Lakes Symposium on VLSI, page 249-252. ACM, (2015)Antennas and Channel Characteristics for Wireless Networks on Chips., , , and . Wireless Personal Communications, 95 (4): 5039-5056 (2017)Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture., , and . ANCS, page 47-56. ACM, (2007)GARUDA: Designing Energy-Efficient Hardware Monitors From High-Level Policies for Secure Information Flow., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (11): 2509-2518 (2018)Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures., , , and . ASP-DAC, page 1-6. IEEE, (2009)SHARP: Shared Heterogeneous Architecture with Reconfigurable Photonic Network-on-Chip., and . ACM J. Emerg. Technol. Comput. Syst., 14 (2): 25:1-25:22 (2018)Secure Model Checkers for Network-on-Chip (NoC) Architectures., , and . ACM Great Lakes Symposium on VLSI, page 45-50. ACM, (2016)Packet security with path sensitization for NoCs., and . DATE, page 1136-1139. IEEE, (2016)Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning., , , and . HPCA, page 480-491. IEEE Computer Society, (2018)Co-design of channel buffers and crossbar organizations in NoCs architectures., , , , and . ICCAD, page 219-226. IEEE Computer Society, (2011)