Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Fitting processor architectures for measurement-based probabilistic timing analysis.

L. Kosmidis, E. Quiñones, J. Abella, T. Vardanega, C. Hernández, A. Gianarro, I. Broster, and F. Cazorla. Microprocess. Microsystems, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Stephanie Hernández

Héctor Hernández

Anja Hernández

Daniel Hernández

Lionel Hernández

Other publications of authors with the same name

Enforcing Predictability of Many-Cores With DCFNoC.T. Picornell, J. Flich, C. Hernández, and J. Duato. IEEE Trans. Computers, 70 (2): 270-283 (2021)Locality-aware cache random replacement policies.P. Benedicte, C. Hernández, J. Abella, and F. Cazorla. J. Syst. Archit., (2019)SafeSU-2: a Safe Statistics Unit for Space MPSoCs.G. Cabo, S. Alcaide, C. Hernández, P. Benedicte, F. Bas, F. Mazzocchetti, and J. Abella. DATE, page 1085-1086. IEEE, (2022)HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem.V. Kostalabros, J. Ribes-González, O. Farràs, M. Moretó, and C. Hernández. FPL, page 52-59. IEEE, (2021)A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.J. Anders, P. Andreu, B. Becker, S. Becker, R. Cantoro, N. Deligiannis, N. Elhamawy, T. Faller, C. Hernández, N. Mentens and 10 other author(s). ETS, page 1-10. IEEE, (2023)Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems.M. Panic, C. Hernández, E. Quiñones, J. Abella, and F. Cazorla. RTAS, page 267-278. IEEE Computer Society, (2016)Resilient random modulo cache memories for probabilistically-analyzable real-time systems.D. Trilla, C. Hernández, J. Abella, and F. Cazorla. IOLTS, page 27-32. IEEE, (2016)Enabling High-Performance Crossbars through a Floorplan-Aware Design.A. Roca, C. Hernández, J. Flich, F. Silla, and J. Duato. ICPP, page 269-278. IEEE Computer Society, (2012)A new mechanism to deal with process variability in NoC links.C. Hernández, F. Silla, V. Santonja, and J. Duato. IPDPS, page 1-11. IEEE, (2009)Random modulo: a new processor cache design for real-time critical systems.C. Hernández, J. Abella, A. Gianarro, J. Andersson, and F. Cazorla. DAC, page 29:1-29:6. ACM, (2016)

BibSonomy

Disambiguation of "Hernández, Carles"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Fitting processor architectures for measurement-based probabilistic timing analysis.

Please choose a person to relate this publication to

Stephanie Hernández

Héctor Hernández

Anja Hernández

Daniel Hernández

Lionel Hernández

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Hernández, Carles"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Fitting processor architectures for measurement-based probabilistic timing analysis.

Please choose a person to relate this publication to

Stephanie Hernández

Héctor Hernández

Anja Hernández

Daniel Hernández

Lionel Hernández

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Fitting processor architectures for measurement-based probabilistic timing analysis.