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Disambiguation of "Yun, Won-Joo"

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A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.

, , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 140-141. IEEE, (2009)

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Won-Tai Yun

Yun-Joo Koh Park

Bettina Yunis

Jong-Mo Yun

Hyong-Sik Yun

 

Other publications of authors with the same name

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface., , , , , , , , , and 3 other author(s). ISSCC, page 280-281. IEEE, (2008)Coverage expandable current type code controlled DCC with TDC-based range selector., , , , and . IEICE Electron. Express, 6 (5): 205-210 (2009)A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme., , , , , and . ESSCIRC, page 82-85. IEEE, (2008)A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL., , , and . ISCAS, page 1576-1579. IEEE, (2013)A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS., , , , , , , , , and 14 other author(s). ISSCC, page 140-141. IEEE, (2009)18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution., , , , , , , , , and 11 other author(s). ISSCC, page 316-317. IEEE, (2016)A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter., , , , and . ISCAS, page 1-4. IEEE, (2009)17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)A 4-bit 2GSamples/s parallel Flash ADC using comb-type reference ladder., , and . IEICE Electron. Express, 5 (15): 562-567 (2008)A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface., , , , , , , , , and 6 other author(s). ISCAS, page 3861-3864. IEEE, (2010)