( en | de | ru )

 

Disambiguation of "Choi, Young-Jung"

Author of the publication

copydeleteadd this publication to your clipboard
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.

, , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 140-141. IEEE, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Young Jung

Young-Soon Choi

Se-Young Choi

Jin-Young Choi

Won-Young Choi

 

Other publications of authors with the same name

A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface., , , , , , , , , and 6 other author(s). ISCAS, page 3861-3864. IEEE, (2010)A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL., , , , , , , , , and 3 other author(s). ISSCC, page 547-556. IEEE, (2006)A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface., , , , , , , , , and 1 other author(s). ISSCC, page 48-50. IEEE, (2012)A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS., , , , , , , , , and 14 other author(s). ISSCC, page 140-141. IEEE, (2009)An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface., , , , , , , and . ISSCC, page 312-313. IEEE, (2013)A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter., , , , and . ISCAS, page 1-4. IEEE, (2009)A 1.5-V 3.2 Gb/s/pin Graphic DDR4 SDRAM With Dual-Clock System, Four-Phase Input Strobing, and Low-Jitter Fully Analog DLL., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 42 (11): 2369-2377 (2007)SDTV Quality Assessment Using Energy Distribution of DCT Coefficients., , , , and . ICESS, page 118-125. IEEE Computer Society, (2008)A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology., , , , , , , , and . ISSCC, page 502-504. IEEE, (2011)Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster., , , and . SoCC, page 79-82. IEEE, (2010)