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Disambiguation of "Yeap, Geoffrey"

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Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes.

, , , , , , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

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Geoffrey Hinds

Geoffrey Coulson

Geoffrey Lund

Geoffrey Davis

Geoffrey Mwachala

 

Other publications of authors with the same name

FinFET based SRAM bitcell design for 32 nm node and below., , and . Microelectron. J., 42 (3): 520-526 (2011)A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology., , , , , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (7): 1023-1032 (2016)A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 56 (1): 179-187 (2021)Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization., , , , , , , , , and 1 other author(s). VLSIC, page 84-. IEEE, (2015)Holistic technology optimization and key enablers for 7nm mobile SoC., , , , , , , , , and 4 other author(s). VLSIC, page 198-. IEEE, (2015)Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes., , , , , , , , , and 4 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Technology-design-manufacturing co-optimization for advanced mobile SoCs.. CICC, page 1-8. IEEE, (2014)15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications., , , , , , , , , and 2 other author(s). ISSCC, page 238-240. IEEE, (2020)-197dBc/Hz FOM 4.3-GHz VCO Using an addressable array of minimum-sized nmos cross-coupled transistor pairs in 65-nm CMOS., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)