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Disambiguation of "Sakimura, Noboru"

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A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.

, , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 4 (4): 460-474 (2014)

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Noboru Yamazaki

Noboru Sonoyama

Noboru Hasegawa

Sergio Noboru Kuriyama

 

Other publications of authors with the same name

MRAM Cell Technology for Over 500-MHz SoC., , , , , , , and . IEEE J. Solid State Circuits, 42 (4): 830-838 (2007)A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing., , , , , , , , , and 5 other author(s). ISCAS, page 1588-1591. IEEE, (2014)Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode., , , , , and . IEICE Trans. Electron., 90-C (2): 531-535 (2007)Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory., , , , and . J. Multiple Valued Log. Soft Comput., 26 (1-2): 125-140 (2016)A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes., , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2013)A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure., , , , , , , and . IEICE Electron. Express, 11 (13): 20140296 (2014)A 16-Mb Toggle MRAM With Burst Modes., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 42 (11): 2378-2385 (2007)MRAM Applications Using Unlimited Write Endurance., , , , and . IEICE Trans. Electron., 90-C (10): 1936-1940 (2007)Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 50 (2): 476-489 (2015)Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating., , , , , , , , , and 4 other author(s). ISSCC, page 194-195. IEEE, (2013)