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Time-Redundant Multiple Computation for Fault-Tolerant Digital Neural Networks.

, , and . ISCAS, page 977-980. IEEE, (1995)

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Merged Arithmetic for Computing Wavelet Transforms., and . Great Lakes Symposium on VLSI, page 196-201. IEEE Computer Society, (1998)VLSI Concurrent Error Correcting Adders and Multipliers., and . DFT, page 287-294. IEEE Computer Society, (1993)A systolic array for 2-D DFT and 2-D DCT., and . ASAP, page 123-131. IEEE, (1994)A Processor for Staggered Interval Arithmetic., and . ASAP, page 104-112. IEEE Computer Society, (1995)An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform., and . ASAP, page 378-388. IEEE Computer Society, (2003)Long Residue Checking for Adders., and . ASAP, page 177-180. IEEE Computer Society, (2012)Multiply-Accumulate Architecture for a Special Class of Optimal Extension Fields., and . ASAP, page 134-139. IEEE Computer Society, (2005)A Spanning Tree Carry Lookahead Adder., and . IEEE Trans. Computers, 41 (8): 931-939 (1992)Implementation of a Single Chip, Pipelined, Complex, One-Dimensional Fast FourierTransform in 0.25 mu m BulkCMOS., , , , and . ASAP, page 335-343. IEEE Computer Society, (2002)Parallel Counters.. IEEE Trans. Computers, 22 (11): 1021-1024 (1973)