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Disambiguation of "Valls, Javier"

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High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (3): 568-573 (2012)

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Javier Valls

Alvaro Valls

Alvaro Valls

Javier Manero

Javier Jáurequi

 

Other publications of authors with the same name

Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems., , , and . CSSP, 38 (4): 1793-1810 (2019)A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems., , , , and . PIMRC, page 531-535. IEEE, (2004)Power analysis and estimation tool integrated with XPOWER., , , and . FPGA, page 259. ACM, (2004)Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs., , , and . VLSI Signal Processing, 47 (2): 183-187 (2007)Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms., and . FPL, page 472-475. IEEE, (2007)Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain., , and . Int. J. Reconfigurable Comput., (2014)Modified Shuffled Based Architecture for High-Throughput Decoding of LDPC Codes., , , and . J. Signal Process. Syst., 68 (2): 139-149 (2012)FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices., , , , , and . IEEE Trans. Educ., 50 (3): 229-235 (2007)Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes., , , and . J. Signal Process. Syst., 66 (2): 99-104 (2012)Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (11): 2256-2267 (2014)