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New SRAM design using body bias technique for ultra low power applications.

, , , , and . ISQED, page 468-471. IEEE, (2010)

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65NM sub-threshold 11T-SRAM for ultra low voltage applications., , , , and . SoCC, page 113-118. IEEE, (2008)Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits., , , and . SoCC, page 259-264. IEEE, (2016)Postsilicon Adaptation for Low-Power SRAM under Process Variation., , , , and . IEEE Des. Test Comput., 27 (6): 26-35 (2010)Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology., , , , , , , and . Microelectron. J., 45 (1): 23-34 (2014)Impact of NBTI on performance of domino logic circuits in nano-scale CMOS., , , and . Microelectron. J., 42 (12): 1327-1334 (2011)An analytical model for read static noise margin including soft oxide breakdown, negative and positive bias temperature instabilities., , , and . Microelectron. Reliab., 53 (5): 670-675 (2013)A low-power SRAM using bit-line charge-recycling technique., , and . ISLPED, page 177-182. ACM, (2007)Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS., and . ISQED, page 342-346. IEEE, (2012)Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies., and . SoCC, page 261-264. IEEE, (2006)Silicon validation of LUT-based logic-locked IP cores., , , , , , , , and . DAC, page 1189-1194. ACM, (2022)