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Disambiguation of "Goel, Sandeep Kumar"

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Circuit Topology-Based Test Pattern Generation for Small-Delay Defects.

, , , , and . Asian Test Symposium, page 307-312. IEEE Computer Society, (2010)

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Sandeep Kumar

Sandeep Kumar

Sandeep Kumar Botla

Sandeep Kumar Parashar

Vishal Goel

 

Other publications of authors with the same name

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 55 (4): 956-966 (2020)Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips., and . J. Electron. Test., 19 (4): 407-416 (2003)A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips., and . J. Electron. Test., 19 (4): 425-435 (2003)Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling., , , and . IEEE Trans. Computers, 58 (3): 409-423 (2009)Accurate measurement of small delay defect coverage of test patterns., , , , and . ITC, page 1-10. IEEE Computer Society, (2009)Efficient observation-point insertion for diagnosability enhancement in digital circuits., , , and . ITC, page 1-10. IEEE, (2015)Hierarchy-aware and area-efficient test infrastructure design for core-based system chips., , , and . DATE, page 285-290. European Design and Automation Association, Leuven, Belgium, (2006)Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track.. ICCAD, page 273. ACM, (2012)Test scheduling for modular SOCs in an abort-on-fail environment., , , and . ETS, page 8-13. IEEE Computer Society, (2005)DfT Architecture for 3D-SICs with Multiple Towers., , , and . ETS, page 51-56. IEEE Computer Society, (2011)