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Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability., and . IEEE Access, (2019)Hardware-oriented succinct-data-structure based on block-size-constrained compression., , and . SoCPaR, page 136-140. IEEE, (2015)Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits., , and . ISVLSI, page 243-248. IEEE Computer Society, (2004)Benchmarks for FPGA-Targeted High-Level-Synthesis., , and . CANDAR, page 232-238. IEEE, (2019)A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects., , and . Systems and Computers in Japan, 28 (2): 54-61 (1997)Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , and . ISMVL, page 17. IEEE Computer Society, (2006)Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction., , and . J. Robotics Mechatronics, 12 (5): 534-540 (2000)Path Planning Based on Distance Transformation and Its VLSI Implementation., and . J. Robotics Mechatronics, 12 (5): 527-533 (2000)An FPGA accelerator for PatchMatch multi-view stereo using OpenCL., , , and . J. Real-Time Image Processing, 17 (2): 215-227 (2020)Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals., , , and . ERSA, page 309-310. CSREA Press, (2008)