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Deeply-scaled CMOS-integrated nanophotonic devices for next generation supercomputers., , , , , and . ACM Great Lakes Symposium on VLSI, page 475-476. ACM, (2011)A 25 Gb/s burst-mode receiver for low latency photonic switch networks., , , , , , , and . OFC, page 1-3. IEEE, (2015)Silicon Photonic Switches Hybrid-Integrated With CMOS Drivers., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 47 (1): 345-354 (2012)A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 50 (12): 3120-3132 (2015)A 3.9ns 8.9mW 4×4 silicon photonic switch hybrid integrated with CMOS driver., , , , , , , , , and 1 other author(s). ISSCC, page 222-224. IEEE, (2011)22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)25Gb/s 3.6pJ/b and 15Gb/s 1.37pJ/b VCSEL-based optical links in 90nm CMOS., , and . ISSCC, page 418-420. IEEE, (2012)Optical receivers using DFE-IIR equalization., , and . ISSCC, page 130-131. IEEE, (2013)A ≪5mW/Gb/s/link, 16×10Gb/s Bi-Directional Single-Chip CMOS Optical Transceiver for Board-Level Optical Interconnects., , , , , , , and . ISSCC, page 294-295. IEEE, (2008)A Throughput-Optimized Optical Network for Data-Intensive Computing., , , , , , , , , and 1 other author(s). IEEE Micro, 34 (5): 52-63 (2014)