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Architectural support for efficient message passing on shared memory multi-cores.

, , , and . J. Parallel Distributed Comput., (2016)

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ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory., , , , and . IEEE Trans. Parallel Distributed Syst., 25 (5): 1359-1369 (2014)Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations., , , , and . MICRO, page 337-349. ACM, (2021)Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory., , , , and . PACT, page 203-204. IEEE Computer Society, (2011)Directory-Based Conflict Detection in Hardware Transactional Memory., , and . HiPC, volume 5374 of Lecture Notes in Computer Science, page 541-554. Springer, (2008)Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems., , , and . PDP, page 221-228. IEEE, (2012)On the interactions between ILP and TLP with hardware transactional memory., , , , and . Microprocess. Microsystems, (2024)DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory., , , and . IEEE Trans. Parallel Distributed Syst., 33 (1): 1-13 (2022)Techniques to improve performance in requester-wins hardware transactional memory., , , , and . ACM Trans. Archit. Code Optim., 10 (4): 42:1-42:25 (2013)Hardware Approaches to Transactional Memory in Chip Multiprocessors., and . Handbook on Data Centers, Springer, (2015)The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems., , , , and . IPDPS Workshops, page 700-707. IEEE, (2011)