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Disambiguation of "Yabuuchi, Makoto"

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A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.

, , , , , , , , , and . A-SSCC, page 17-20. IEEE, (2016)

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Makoto Yamamoto

Makoto Nakamura

Makoto Arai

Makoto Ida

Makoto Kobayashi

 

Other publications of authors with the same name

A stable chip-ID generating physical uncloneable function using random address errors in SRAM., , , , , , and . SoCC, page 143-147. IEEE, (2012)A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 42 (4): 820-829 (2007)A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (11): 2335-2344 (2018)28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 22 (3): 575-584 (2014)A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2., , , and . VLSI Circuits, page 248-. IEEE, (2019)A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die., , , , , , , , , and 7 other author(s). ISSCC, page 488-617. IEEE, (2007)A cost-effective 45nm 6T-SRAM reducing 50mV Vmin and 53% standby leakage with multi-Vt asymmetric halo MOS and write assist circuitry., , , , , , and . ISQED, page 438-441. IEEE, (2013)A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline., , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). ISSCC, page 326-606. IEEE, (2007)12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM., , , and . VLSI Circuits, page 19-20. IEEE, (2018)