( en | de | ru )

 

Disambiguation of "Nii, Koji"

Author of the publication

copydeleteadd this publication to your clipboard
A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry.

, , , , , , , , , and . A-SSCC, page 17-20. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Koji Kameo

Koji Onoda

Koji Ota

Tomoko Kojima

Seth Nii-Annang

 

Other publications of authors with the same name

FEOL/BEOL wear-out estimator using stress-to-frequency conversion of voltage/temperature-sensitive ring oscillators for 28nm automotive MCUs., , , , , and . ESSCIRC, page 265-268. IEEE, (2016)A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 42 (4): 820-829 (2007)A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure., , , , , and . ISCAS (1), page 73-76. IEEE, (2005)A stable chip-ID generating physical uncloneable function using random address errors in SRAM., , , , , , and . SoCC, page 143-147. IEEE, (2012)Design Challenges in 3-D SoC Stacked With a 12.8 GB/s TSV Wide I/O DRAM., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 364-372 (2016)A 28nm High-κ metal-gate single-chip communications processor with 1.5GHz dual-core application processor and LTE/HSPA+-capable baseband processor., , , , , , , , , and 5 other author(s). ISSCC, page 156-157. IEEE, (2013)A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (11): 2335-2344 (2018)28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 22 (3): 575-584 (2014)Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory., , , , , , , , , and 47 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 27 (2): 253-280 (2019)Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (8): 1359-1365 (2012)