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An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC., , , , and . IEEE Trans. Ind. Informatics, 9 (1): 487-501 (2013)Multilevel MPSoC Performance Evaluation Using MDE Approach., , , , and . SoC, page 1-4. IEEE, (2006)Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System., , and . FCCM, page 165. IEEE Computer Society, (2015)An efficient power estimation methodology for complex RISC processor-based platforms., , , , and . ACM Great Lakes Symposium on VLSI, page 239-244. ACM, (2012)ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures., , , , and . Int. J. Reconfigurable Comput., (2019)Dynamic reconfiguration of modular I/O IP cores for avionic applications., , , , and . ReConFig, page 1-6. IEEE, (2012)Communication-centric design for FMC based I/O system., , , and . ReCoSoC, page 1-8. IEEE, (2014)A Comparative Study of Sorting Algorithms with FPGA Acceleration by High Level Synthesis., , , and . Computación y Sistemas, 23 (1): 213 (2019)An Optimized Software Radio Application Using a Dynamic Slack Reclamation Technique on a Real Platform OMAP 3530., , and . AICCSA, page 637-644. IEEE Computer Society, (2017)PETS: Power and energy estimation tool at system-level., , , , , and . ISQED, page 535-542. IEEE, (2014)