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Disambiguation of "Yun, Tae Sik"

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18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.

, , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 318-319. IEEE, (2016)

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Tae-Sik Park

Hyong-Sik Yun

Jong-Mo Yun

Jaeman Yun

Yong-Seon Yun

 

Other publications of authors with the same name

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , and 39 other author(s). ISSCC, page 444-446. IEEE, (2022)18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface., , , , , , , , , and 12 other author(s). ISSCC, page 318-319. IEEE, (2016)High bandwidth memory(HBM) with TSV technique., , , , , , , , , and 9 other author(s). ISOCC, page 181-182. IEEE, (2016)22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST., , , , , , , , , and 27 other author(s). ISSCC, page 334-336. IEEE, (2020)A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization., , , , , , , , , and 29 other author(s). IEEE J. Solid State Circuits, 58 (1): 256-269 (2023)13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization., , , , , , , , , and 38 other author(s). ISSCC, page 238-240. IEEE, (2024)