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Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs.

, , , , and . DAC, page 190:1-190:6. ACM, (2014)

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Optimizing SDRAM bandwidth for custom FPGA loop accelerators., and . FPGA, page 195-204. ACM, (2012)GPU vs FPGA: A Comparative Analysis for Non-standard Precision., , and . ARC, volume 8405 of Lecture Notes in Computer Science, page 298-305. Springer, (2014)Compiling Higher Order Functional Programs to Composable Digital Hardware., , , , , , and . FCCM, page 234. IEEE Computer Society, (2014)Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS., , and . FCCM, page 159-162. IEEE Computer Society, (2015)Analytical synthesis of bandwidth-efficient SDRAM address generators., and . Microprocess. Microsystems, 36 (8): 665-675 (2012)Survey of domain-specific languages for FPGA computing., and . FPL, page 1-12. IEEE, (2016)Application Specific Memory Access, Reuse and Reordering for SDRAM., and . ARC, volume 6578 of Lecture Notes in Computer Science, page 41-52. Springer, (2011)Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine., , , , and . HPEC, page 1-10. IEEE, (2020)High-level synthesis of dynamic data structures: A case study using Vivado HLS., , and . FPT, page 362-365. IEEE, (2013)FPGA-based K-means clustering using tree-based data structures., , and . FPL, page 1-6. IEEE, (2013)