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Disambiguation of "Pereira, Monica Magalhães"

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A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility.

, , , , , and . J. Signal Process. Syst., 85 (1): 45-66 (2016)

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Roberto Magalhães Paniago

Léo Pini Magalhães

Antonio Carlos Melo Magalhães

Sílvia Maria Magalhães Carvalho

Mateus Simão Saldanha Magalhães

 

Other publications of authors with the same name

Adaptive Processing Architectures for the Ultimate Scaling of the CMOS World., and . ERSA, page 91-97. CSREA Press, (2009)An investigation of latency prediction for NoC-based communication architectures using machine learning techniques., , , and . J. Supercomput., 75 (11): 7573-7591 (2019)Dynamic Reconfigurable Computing: The Alternative to Homogeneous Multicores under Massive Defect Rates., and . Int. J. Reconfigurable Comput., (2011)Generation of Application Specific Fault Tolerant Irregular NoC Topologies Using Tabu Search., , , and . SBESC, page 1-8. IEEE, (2019)Using evolutionary metaheuristics to solve the mapping and routing problem in networks on chip., , , , and . Des. Autom. Embed. Syst., 27 (1-2): 51-83 (June 2023)Mapping Wired Links in a Hybrid Wired-Wireless Network-on-Chip., , , , and . SBESC, page 1-8. IEEE, (2020)Design Space Exploration Using UTNoCs and Genetic Algorithm., , , and . SBESC, page 198-202. IEEE Computer Society, (2016)A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design., , , , and . Trans. High Perform. Embed. Archit. Compil., (2019)Communication Latency Evaluation on a Software-Defined Network-on-Chip., , , and . SBESC, page 1-7. IEEE, (2019)Regression Ensembles for Fast Design Space Exploration of Heterogeneous Hardware Designs., , and . ICMLA, page 201-204. IEEE, (2020)