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Digitally-Controlled Analogue Signal Processing and Conversion Techniques Employing a Logarithmic Building Block.

, and . ISCAS, page 377-380. IEEE, (1994)

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Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity., , and . ISCAS (2), page 57-60. IEEE, (1999)High-speed D/A Conversion with Linear Phase Sin x/x Compensation., and . ISCAS, page 1204-1207. IEEE, (1993)Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output., , , and . ISCAS (1), page 129-132. IEEE, (2003)A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems., , and . ISCAS (1), page 320-323. IEEE, (2001)Digitally-Controlled Analogue Signal Processing and Conversion Techniques Employing a Logarithmic Building Block., and . ISCAS, page 377-380. IEEE, (1994)A CMOS 1.0-μm two-dimensional analog multirate system for real-time image processing., and . IEEE J. Solid State Circuits, 32 (7): 1037-1048 (1997)A high-speed programmable CMOS interface system combining D/A conversion and FIR filtering., and . IEEE J. Solid State Circuits, 29 (8): 972-977 (August 1994)A CMOS logarithmic pipeline A/D converter with a dynamic range of 80 dB., , and . ICECS, page 193-196. IEEE, (2002)A quadrature IF mixer with high image rejection for continuous-time complex Sigma-Delta modulators., , , and . ISCAS (4), page 221-224. IEEE, (2002)A quadrature sampling scheme with improved image rejection for complex-IF receivers., , and . ISCAS (1), page 45-48. IEEE, (2001)