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Improving the Accuracy of Test Compaction through Adaptive Test Update., and . ITC, page 1. IEEE Computer Society, (2008)Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling., , , , , and . ITC, page 1-10. IEEE Computer Society, (2014)Maintaining Accuracy of Test Compaction through Adaptive Re-learning., and . VTS, page 257-263. IEEE Computer Society, (2009)Synthesis of Self-Testing Finite State Machines from High-Level Specifications., , and . ITC, page 757-766. IEEE Computer Society, (1996)Efficient built-in self test of regular logic characterization vehicles., and . VTS, page 1-6. IEEE Computer Society, (2015)The input pattern fault model and its application., and . ED&TC, page 628. IEEE Computer Society, (1997)Physically-Aware N-Detect Test Pattern Selection., , , and . DATE, page 634-639. ACM, (2008)Characterization of Locked Sequential Circuits via ATPG., , , and . ITC-Asia, page 97-102. IEEE, (2019)Modeling the Economics of Testing: A DFT Perspective., , , , and . IEEE Des. Test Comput., 19 (1): 29-41 (2002)Defect Modeling Using Fault Tuples., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (11): 2450-2464 (2006)