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Rapid C to FPGA Prototyping with Multithreaded Emulation Engine.

S. Chen, B. Wang, T. Lin, and C. Liu. ISCAS, page 409-412. IEEE, (2007)

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Christopher Tay

Sarab Tay

Lin Lin

Other publications of authors with the same name

Variation-aware and adaptive-latency accesses for reliable low voltage caches.P. Wang, W. Cheng, Y. Yu, T. Kao, C. Tsai, P. Chang, T. Lin, J. Wang, and T. Chen. VLSI-SoC, page 358-363. IEEE, (2013)Near-Threshold CORDIC Design with Dynamic Circuitry for Long-Standby IoT Applications.P. Chou, Y. Fang, B. Chen, C. Liu, T. Lin, and J. Wang. SoCC, page 250-253. IEEE, (2018)A Low-Area, Low-Power, and Low-Leakage Error-Detecting Latch for Timing-Error Resilient System Designs.C. Liu, Z. Chang, S. Wei, J. Wang, and T. Lin. SoCC, page 1-6. IEEE, (2018)Improving energy efficiency of functional units by exploiting their data-dependent latency.S. Ou, Y. Lin, T. Lin, and C. Liu. ISCAS, page 4165-4168. IEEE, (2010)An efficient 2-D DWT architecture via resource cycling.T. Lin, and C. Jen. ISCAS (4), page 914-917. IEEE, (2001)Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors.P. Wang, S. Tsai, R. Tanjung, T. Lin, J. Wang, and T. Chen. Integr., (2016)Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations.P. Wang, W. Cheng, Y. Yu, T. Kao, C. Tsai, P. Chang, T. Lin, J. Wang, and T. Chen. IEEE Trans. Circuits Syst. II Express Briefs, 63-II (10): 969-973 (2016)ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures.P. Wang, Y. Chien, S. Tsai, X. Lin, R. Tanjung, Y. Lin, S. Syu, T. Lin, J. Wang, and T. Chen. IEEE Trans. Very Large Scale Integr. Syst., 25 (12): 3341-3354 (2017)A 0.21V 40nm NAND-ROM for IoT Sensing Systems with Long Standby Periods.J. Wang, C. Xue, C. Liu, and T. Lin. ISCAS, page 1-4. IEEE, (2020)A Compact DSP Core with Static Floating-Point Arithmetic.T. Lin, H. Lin, C. Chao, C. Liu, and C. Jen. VLSI Signal Processing, 42 (2): 127-138 (2006)

BibSonomy

Disambiguation of "Lin, Tay-Jyi"

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Rapid C to FPGA Prototyping with Multithreaded Emulation Engine.

Please choose a person to relate this publication to

Christopher Tay

Sarab Tay

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Tay-Jyi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Rapid C to FPGA Prototyping with Multithreaded Emulation Engine.

Please choose a person to relate this publication to

Christopher Tay

Sarab Tay

Lin Lin

Lin Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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APA
Chicago
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Rapid C to FPGA Prototyping with Multithreaded Emulation Engine.