Author of the publication

Design of a high speed reverse converter for a new 4-moduli set residue number system.

, , and . ISCAS (4), page 520-523. IEEE, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Srikanthan, Thambipillai
add a person with the name Srikanthan, Thambipillai
 

Other publications of authors with the same name

Optimizing Scaling Factor Computations in Flat Cordic., and . Journal of Circuits, Systems, and Computers, 11 (1): 17-34 (2002)Low-complexity pruning for accelerating corner detection., , , and . ISCAS, page 1684-1687. IEEE, (2012)Partial rerouting algorithm for reconfigurable VLSI arrays., and . ISCAS (5), page 641-644. IEEE, (2003)Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs., , and . Journal of Circuits, Systems, and Computers, (2014)Instruction set customization for area-constrained FPGA designs., , , and . SoCC, page 329-334. IEEE, (2011)Preprocessing technique for accelerating reconfiguration of degradable VLSI arrays., , , and . ISCAS, page 2424-2427. IEEE, (2013)Vector quantization techniques for GMM based speaker verification., , , and . ICASSP (2), page 65-68. IEEE, (2003)Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs., , , and . ReConFig, page 1-8. IEEE, (2018)Rapid estimation of DSPs utilization for efficient high-level synthesis., , and . DSP, page 1261-1265. IEEE, (2015)High-throughput image rotation using sign-prediction based redundant cordic algorithm., , and . ICIP, page 2833-2836. IEEE, (2004)