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Disambiguation of "Huang, Xuan-Lun"

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Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input.

, , and . ASP-DAC, page 775-780. IEEE, (2009)

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Xuan Huang

Shao-Lun Huang

Haibo Xuan

Zhengrong Xuan

Yue Xuan

 

Other publications of authors with the same name

An ADC/DAC loopback testing methodology by DAC output offsetting and scaling., and . VTS, page 289-294. IEEE Computer Society, (2010)Histogram-Based Calibration of Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs., , , and . J. Electron. Test., 27 (4): 441-453 (2011)FPGA-Based Subset Sum Delay Lines., , , and . ATS, page 287-291. IEEE Computer Society, (2014)Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input., , and . ASP-DAC, page 775-780. IEEE, (2009)An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing., , and . Asian Test Symposium, page 367-372. IEEE Computer Society, (2009)A 58.9-dB ACR, 85.5-dB SBA, 5-26-MHz Configurable-Bandwidth, Charge-Domain Filter in 65-nm CMOS., , , and . IEEE J. Solid State Circuits, 48 (11): 2827-2838 (2013)An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration., , , , , , , and . J. Electron. Test., 28 (5): 705-722 (2012)A Scalable Photonic Computer Solving the Subset Sum Problem., , , , , , , , and . CoRR, (2020)ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling., and . IEEE Trans. Very Large Scale Integr. Syst., 19 (10): 1765-1774 (2011)A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager., , , , , and . ETS, page 39-44. IEEE Computer Society, (2011)