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A Quantitative Study of the On-Chip Network and Memory Hierarchy Design for Many-Core Processor.

, , , , and . ICPADS, page 689-696. IEEE Computer Society, (2008)

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Circuit implementation of floating point range reduction for trigonometric functions., , , , , and . ISCAS, page 3010-3013. IEEE, (2007)An efficient scheduling algorithm for dataflow architecture using loop-pipelining., , , , , , , and . Inf. Sci., (2021)RISC-NN: Use RISC, NOT CISC as Neural Network Hardware Infrastructure., , , , , , , , , and 2 other author(s). CoRR, (2021)Characterizing and Understanding Distributed GNN Training on GPUs., , , , , , and . CoRR, (2022)An efficient dataflow accelerator for scientific applications., , , , , , , and . Future Gener. Comput. Syst., (2020)Tackling Variabilities in Autonomous Driving., , , , , , , and . CoRR, (2021)A synergistic reinforcement learning-based framework design in driving automation., , , , , and . Comput. Electr. Eng., (2022)HiHGNN: Accelerating HGNNs through Parallelism and Data Reusability Exploitation., , , , , , , , , and 1 other author(s). CoRR, (2023)Simple and Efficient Heterogeneous Graph Neural Network., , , , and . AAAI, page 10816-10824. AAAI Press, (2023)Streamline Ring ORAM Accesses through Spatial and Temporal Optimization., , , , , , and . HPCA, page 14-25. IEEE, (2021)