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Feedforward compensation technique for all digital phase locked loop based synthesizers., , and . ISCAS, IEEE, (2006)A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration., , , , , and . IEEE J. Solid State Circuits, 49 (1): 50-60 (2014)A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC., , , and . IEEE J. Solid State Circuits, 51 (10): 2345-2356 (2016)RF Variable-Gain Amplifiers and AGC Loops for Digital TV Receivers., , , , , , and . IEICE Trans. Electron., 91-C (6): 854-861 (2008)The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time., and . IEICE Trans. Electron., 90-C (6): 1165-1171 (2007)A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits., , and . IEICE Trans. Electron., 101-C (4): 224-232 (2018)A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter., , and . IEICE Trans. Electron., 90-C (6): 1311-1314 (2007)Analog IC Technologies for Future Wireless Systems.. IEICE Trans. Electron., 89-C (4): 446-454 (2006)Tunable CMOS Power Amplifiers for Reconfigurable Transceivers., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (11): 2394-2401 (2011)A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator., , , , , and . IEEE J. Solid State Circuits, 45 (4): 697-706 (2010)