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Reuse-based test access and integrated test scheduling for network-on-chip.

, , and . DATE, page 303-308. European Design and Automation Association, Leuven, Belgium, (2006)

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Signal Transition Graph Transformations for Initializability., , , and . EDAC-ETC-EUROASIC, page 670. IEEE Computer Society, (1994)RTRAM: Reconfigurable and Testable Multi-Bit RAM Design., and . ITC, page 263-278. IEEE Computer Society, (1988)ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management., and . JETC, 6 (2): 8:1-8:26 (2010)Roll-Forward Checkpointing Schemes., , and . Hardware and Software Architectures for Fault Tolerance, volume 774 of Lecture Notes in Computer Science, page 95-116. Springer, (1993)On the Design and Optimization of a Quantum Polynomial-Time Attack on Elliptic Curve Cryptography., , , and . TQC, volume 5106 of Lecture Notes in Computer Science, page 96-104. Springer, (2008)High defect tolerant low cost memory chips., , and . SoCC, page 119-122. IEEE, (2007)Improved decoding algorithm for high reliable reed muller coding., and . SoCC, page 95-98. IEEE, (2007)Matrix Codes for Reliable and Cost Efficient Memory Chips., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (3): 420-428 (2011)NiVER: Non Increasing Variable Elimination Resolution for Preprocessing SAT instances., and . SAT, (2004)DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM., , , and . J. Low Power Electron., 6 (3): 390-400 (2010)