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Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization.

, , , , , , and . ASP-DAC, page 549-553. IEEE, (2017)

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Modem floorplanning with abutment and fixed-outline constraints., , , and . ISCAS (6), page 6214-6217. IEEE, (2005)Effective power network prototyping via statistical-based clustering and sequential linear programming., , , , , and . DATE, page 1701-1706. EDA Consortium San Jose, CA, USA / ACM DL, (2013)More Effective Power Network Prototyping by Analytical and Centroid Learning., , , , and . ISCAS, page 1-5. IEEE, (2019)Enabling inter-die co-optimization in 3-D IC with TSVs., , , , and . VLSI-DAT, page 1-4. IEEE, (2013)Noise-Aware Floorplanning for Fast Power Supply Network Design., , , , and . ISCAS, page 2028-2031. IEEE, (2007)3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement., and . ISQED, page 129-134. IEEE, (2011)Non-slicing floorplans with boundary constraints using generalized polish expression., , and . ASP-DAC, page 342-345. ACM, (2003)A New Methodology for Noise Sensor Placement Based on Association Rule Mining., , , , , and . ACM Great Lakes Symposium on VLSI, page 81-86. ACM, (2016)Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm., , and . Journal of Circuits, Systems, and Computers, 15 (1): 107-128 (2006)Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization., , , , , , and . ASP-DAC, page 549-553. IEEE, (2017)