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Heterogeneous chip power delivery modeling and co-synthesis for practical 3DIC realization.

, , , , , , and . ASP-DAC, page 549-553. IEEE, (2017)

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Pruned Three-Dimensional Toroidal Networks., and . Inf. Process. Lett., 68 (4): 179-183 (1998)Scalability of Programmable FIR Digital Filters., and . VLSI Signal Processing, 21 (1): 31-35 (1999)Tight Bounds on the Diameter of Gaussian Cubes., and . Comput. J., 41 (1): 52-56 (1998)Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (2): 207-219 (2014)Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs., , , , , , , and . ATS, page 143-148. IEEE Computer Society, (2014)FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment., , , , , , , , , and 1 other author(s). MTDT, page 28-33. IEEE Computer Society, (2006)Worst-case IR-drop monitoring with 1GHz sampling rate., , , and . VLSI-DAT, page 1-4. IEEE, (2013)A Unified Formulation of Honeycomb and Diamond Networks., and . IEEE Trans. Parallel Distributed Syst., 12 (1): 74-80 (2001)Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (8): 1346-1356 (2011)Comparing four classes of torus-based parallel architectures: Networkparameters and communication performance., and . Math. Comput. Model., 40 (7-8): 701-720 (2004)