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An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler., , , , , , , , , and 6 other author(s). ISSCC, page 90-91. IEEE, (2008)Software-cooperative power-efficient heterogeneous multi-core for media processing., , , , , , , , , and 1 other author(s). ASP-DAC, page 736-741. IEEE, (2008)Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation., , , , , and . IEICE Trans. Electron., 95-C (12): 1872-1882 (2012)Foreword.. IEICE Trans. Electron., 94-C (4): 385 (2011)A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption., , , , , , , , , and 4 other author(s). ISSCC, page 100-590. IEEE, (2007)A PA-RISC Mikroprocessor PA/50L For Low-Cost Systems., , , , , , , , , and 9 other author(s). COMPCON, page 47-52. IEEE Computer Society, (1994)Guest Editors' Introduction: Energy-Efficient Design., and . IEEE Micro, 25 (5): 6-9 (2005)SH4 RISC multimedia microprocessor., , , and . IEEE Micro, 18 (2): 26-34 (1998)Power-Efficient Heterogeneous Multicore Technology for Digital Convergence.. Asia-Pacific Computer Systems Architecture Conference, volume 4697 of Lecture Notes in Computer Science, page 2-3. Springer, (2007)Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction., , , , , , , and . Systems and Computers in Japan, 36 (6): 39-48 (2005)