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Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers.

, , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)

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DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers., , , , , and . IEEE J. Solid State Circuits, 52 (4): 1134-1143 (2017)The Study of a Dual-Mode Ring Oscillator., and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (4): 210-214 (2011)14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB., , , , , , , , , and 1 other author(s). ISSCC, page 1-3. IEEE, (2015)2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 36-37. IEEE, (2016)An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (10): 934-938 (2016)The Design and Analysis of Dual-Delay-Path Ring Oscillators., and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (3): 470-478 (2011)An all-digital de-skew clock generator for arbitrary wide range delay., , , and . APCCAS, page 112-115. IEEE, (2010)Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers., , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices., , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)