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An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.

, , , , , and . DATE, page 1128. IEEE Computer Society, (2002)

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Voltage island management in near threshold manycore architectures to mitigate dark silicon., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Floorplan-aware hierarchical NoC topology with GALS interfaces., , , , , , and . ISCAS, page 652-655. IEEE, (2012)Floorplanning-aware design space exploration for application-specific hierarchical networks on-chip., , , , , , and . NoCArc@MICRO, page 31-36. ACM, (2011)Design Space Pruning and Computational Workload Splitting for Autotuning OpenCL Applications., , , and . RAPIDO, page 4:1-4:6. ACM, (2018)A security monitoring service for NoCs., , and . CODES+ISSS, page 197-202. ACM, (2008)An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods., , and . ICSAMOS, page 150-157. IEEE, (2008)Dynamic configuration of application-specific implicit instructions for embedded pipelined processors., , and . SAC, page 1509-1516. ACM, (2008)Energy estimation and optimization of embedded VLIW processors based on instruction clustering., , , , , and . DAC, page 886-891. ACM, (2002)Two-levels of adaptive buffer for virtual channel router in NoCs., , , , , and . VLSI-SoC, page 302-307. IEEE, (2011)An industrial design space exploration framework for supporting run-time resource management on multi-core systems., , , , , , and . DATE, page 196-201. IEEE Computer Society, (2010)