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Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge., and . IEICE Trans. Inf. Syst., 88-D (7): 1389-1396 (2005)The O-Sequence: Representation of 3D-Dissection., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (8): 2111-2119 (2008)Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (4): 659-668 (2007)Subresolution Assist Feature Generation With Supervised Data Learning., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1225-1236 (2018)Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (5): 753-765 (2015)Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair., and . ASP-DAC, page 331-337. ACM, (2003)Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern., , , and . DATE, page 241-244. IEEE, (2016)Lithography hotspot detection by two-stage cascade classifier using histogram of oriented light propagation., , , and . ASP-DAC, page 81-86. IEEE, (2017)Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement., , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2017)A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation., , and . DATE, page 49-54. IEEE, (2016)